This is stars and forks stats for /Wevel/ExperiarSoC repository. As of 28 Apr, 2024 this repository has 10 stars and 1 forks.
ExperiarSoC RISC-V SoC designed for the Efabless Open MPW Program. This project Features Dual RV32I cores Per core SRAM JTAG interface External flash controller Shared video SRAM Configurable VGA output 3x UART ports + 1 internal to caravel 1x SPI ports 4x PWM counters with 4x separate outputs (2 are internal read only) Memory Map Macro Layout Build Status CaravelHost: Success ExperiarCore: Success Flash: Success Peripherals: Success Video: Success WishboneInterconnect: Success user_project_wrapper:...
ExperiarSoC RISC-V SoC designed for the Efabless Open MPW Program. This project Features Dual RV32I cores Per core SRAM JTAG interface External flash controller Shared video SRAM Configurable VGA output 3x UART ports + 1 internal to caravel 1x SPI ports 4x PWM counters with 4x separate outputs (2 are internal read only) Memory Map Macro Layout Build Status CaravelHost: Success ExperiarCore: Success Flash: Success Peripherals: Success Video: Success WishboneInterconnect: Success user_project_wrapper:...
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