ucb-bar/riscv-sodor

educational microarchitectures for risc-v isa

ScalaPythonMakefileAssemblyVerilogM4
This is stars and forks stats for /ucb-bar/riscv-sodor repository. As of 29 Mar, 2024 this repository has 602 stars and 151 forks.

About The Sodor Processor Collection Note: This repo has been updated to be used with the Chipyard SoC Generator. For the old self-contained version of Sodor (which is no longer maintained), see https://github.com/ucb-bar/riscv-sodor/tree/sodor-old. Diagrams: Sodor Github wiki More documentation: Librecores Sodor wiki Downstream development: Librecores Sodor This repo has been put together to demonstrate a number of simple RISC-V integer pipelines written in Chisel: 1-stage (essentially an ISA simulator) 2-stage...
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