pulp-platform/common_verification

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Common Verification This repository contains commonly used SystemVerilog modules and classes for verification. This code is generally not synthesizable. Contents Basic Modules Name Description Status clk_rst_gen Standalone clock and reset generator active sim_timeout Timeout for simulations active stream_watchdog Terminates a simulation after a number of cycles of inactivity of a stream active Generic Functions and Tasks rand_verif_pkg defines the following functions and tasks: Name Description Status rand_wait Wait...