UVVM/UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

VHDLHTMLPythonStataJavaScriptShellOther
This is stars and forks stats for /UVVM/UVVM repository. As of 19 Apr, 2024 this repository has 305 stars and 79 forks.

UVVM UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches. Overview, Readability, Maintainability, Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 to handle exactly these aspects. Full documentation can be found on https://uvvm.github.io. UVVM consists currently of the following elements: Utility Library VVC...
Read on GithubGithub Stats Page
repotechsstarsweeklyforksweekly
Shougo/deol.nvimVim ScriptTypeScriptPython3240160
reoreo-zyt/blogVueJavaScriptCSS32000
jzfai/vue3-admin-templateJavaScriptVueSCSS2870870
banteg/yearn-feesVyperPython30010
ET-Team/EnigTech2ZenScriptHTMLJavaScript1460370
craftzdog/link-in-bioHTMLCSS147078-1
Tinkerforge/warp-chargerHTMLJavaScriptTeX45070
exadel-inc/CompreFaceJavaTypeScriptPython3.3k04750
bootstrap-vue/bootstrap-vueJavaScriptSCSSShell14.4k01.9k0
hiukim/mind-ar-jsJavaScriptHTMLOther1.8k03240