This is stars and forks stats for /SpinalHDL/NaxRiscv repository. As of 23 Apr, 2024 this repository has 177 stars and 29 forks.
NaxRiscv An RISC-V core currently characterised by : Out of order execution with register renaming Superscalar (ex : 2 decode, 3 execution units, 2 retire) (RV32/RV64)IMAFDCSU (Linux / Buildroot works on hardware) High perf config : 2.93 DMIPS/Mhz, 5.02 Coremark/Mhz, 1.67 Embench-iot baseline (Cortex M4) @ 155 Mhz + 13.3 KLUT on Artix 7-3 Portable HDL, but target FPGA with distributed ram (Xilinx series 7 is the reference used so far) Target a (relatively) low area usage and high fmax (not the best...
NaxRiscv An RISC-V core currently characterised by : Out of order execution with register renaming Superscalar (ex : 2 decode, 3 execution units, 2 retire) (RV32/RV64)IMAFDCSU (Linux / Buildroot works on hardware) High perf config : 2.93 DMIPS/Mhz, 5.02 Coremark/Mhz, 1.67 Embench-iot baseline (Cortex M4) @ 155 Mhz + 13.3 KLUT on Artix 7-3 Portable HDL, but target FPGA with distributed ram (Xilinx series 7 is the reference used so far) Target a (relatively) low area usage and high fmax (not the best...
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