EIE2-IAC-Labs/Project_Brief

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ADIC MSc (2022 - 2023) Team Project - RISC-V RV32I Processor Peter Cheung, V2.0 - 29 June 2023 Objectives To learn RISC-V 32-bit integer instruction set architecture To implememnt a single-cycle RV32I instruction set in a microarchitecture To implemententing the F1 starting light algorithm in RV32I assembly language To verify your RV32I design by executing the F1 light program As stretched goal, to implement a simple pipelined version of the microarchitecutre with or without hazard unit As a further...